With great strides of IT technology, general purpose computers such as servers etc. have been recognized as a part of social infrastructures, and the market demand for improved performance and power saving operations of computers has been increased. The demand is similarly growing for the CPU (Central Processing Unit) of a computer.
Conventionally, the performance of the CPU has been attained by improving the instruction processing from an in-order execution system to an out-of-order execution system, improving an instruction processing circuit with the advances of semiconductor technology, and using high frequencies for higher operation speeds. However, with the advanced microfabrication technology for semiconductors, strict requirements have been imposed on the power consumption for operations and the growth of the ratio of the performance to the increasing number of transistors has been slowing. Therefore, it has become more difficult to solve the current problems by means of the conventional workarounds.
In this situation, there have been various apparatuses by, for example, applying a plurality of cores in a CPU, processing a plurality of instruction threads in a core, etc. There are systems such as a VMT (Vertical Multi-Thread system), an SMT (Simultaneous Multi-Thread system), etc. for processing a plurality of instruction threads in a core.
The VMT is advantageous in processing a plurality of instruction threads by adding a relatively small number of transistors, but cannot simultaneously process a plurality of threads, thereby incurring a penalty when thread switching occurs.
The SMT does not incur the thread switching unlike the VMT, but requires a larger number of transistors to be added, and when a circuit is used to share transistors between threads to reduce the number of transistors, there occurs an outstanding influence between the threads that the delay of processing in one thread affects the processing in another thread. Especially, the SMT requires a larger number of transistors and causes the problem that the increased transistors have to be more efficiently used.
The patent document 1 discloses the technology of a state machine in a multi-thread processor. The patent document 2 discloses the memory corresponding to a multi-thread system. The patent documents 3 and 4 disclose the technology of accessing an erroneous thread.                [Patent Document 1] National Publication of International Patent Application No. 2003-516570        [Patent Document 2] Japanese Laid-open Patent Publication No. 10-97461        [Patent Document 3] Japanese Laid-open Patent Publication No. 2002-108630        [Patent Document 4] Japanese Laid-open Patent Publication No. 2002-123402        